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Improving the Long-Term Reliability of Digital Organic Circuits (ILDOC)


Project description

The main objective of the proposed research project is to improve the applicability of organic circuits in real-life applications by increasing the expected circuit lifetime. We intend to tackle the pressing issue of circuit aging with two main strategies, which require innovations both on technological issues as well as on circuit design aspects: First, by increasing the number of feasible topologies by means of improving the organic n-channel devices whilst in parallel optimizing the digital gate topologies. On the side of the circuit design, this will require the first reported systematic characterization, evaluation and optimization of possible gate topologies with regard to aging-aware reliability. As key result, we aim to find and implement the most promising candidates for gate design with the lowest susceptibility to the parameter shifts induced by device aging. We evaluate the exposure of the critical devices to gate bias stress, which is the most critical parameter for device aging. A major impediment for the design of gates in current organic technologies is the strong asymmetry between p- and n-channel transistor performance. To widen the design space available for circuit design, we therefore aim to improve the n-channel transistor performance in terms of mobility and bias stress stability to bring it closer to the one of the p-channel device. Incorporation of new semiconductor materials and optimization of the fabrication process will be necessary to achieve this goal. As a parallel approach and second strategy for circuit lifetime enhancement, we will for the first time explore the prospects of low-voltage design in organic circuits. As device aging exhibits an exponential dependence on the gate bias levels, the reduction of supply voltage is on the one hand an extremely promising approach for lifetime improvement. On the other hand, process variability (matching) hinders operation at low voltages. This will again require careful evaluation of gate topologies to find the most promising candidates for low-voltage operation. Furthermore, the optimum supply voltage with respect to reliability, the necessary performance trade-offs and the achievable improvements in circuit lifetime will need to be investigated. In parallel, the transistor device engineering will be optimized specifically for operation at low supply voltages. This will require a better understanding of the trade-offs that come with the use of different gate dielectrics and the corresponding differing material properties, especially regarding parameters like mobility, threshold voltage and bias stress stability. This range of devices will be used in the circuit-level analysis, which on one hand will considerably broaden the design space for circuit design; on the other hand, it will also allow an evaluation of transistor implementations which offer the best performance trade-off from a circuit point of view.

Start/End of project

01.01.2019 until 31.12.2021

Project manager

Prof. Dr.-Ing. Y. Manoli

Contact person

M. Sc. Xavier Cuignet
Phone:+49 (0) 761 / 203 - 67563


Dr. Hagen Klauk, Max Planck Institute for Solid State Research


Deutsche Forschungsgemeinschaft
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